1. Field of the Invention
The present invention relates to integrated circuit fabrication and, more particularly, to structures and methods for interconnecting dies and substrates.
2. Description of Related Art
In many applications, it is necessary to provide intimate contact between a semiconductor device and the substrate to which it is mounted. Intimate contact is needed to assure a sufficient electrical connection and also sufficient thermal conductivity.
One example of the foregoing "applications" involves multilayer ceramic (MLC) technology. To overcome the limitations and the expense of MLC technology for high-performance systems, silicon wafers have heretofore been used as substrates for thin-film interconnection modules. Such silicon PC boards (SiPCBs) can provide very precise, high-density interconnects with a minimal number of metal levels. With sufficient metallization thickness, near transmission-line quality interconnects have been achieved over wafer-scale distances. SiPCBs also have very good thermal and mechanical characteristics; for example, they are virtually immune to thermal stresses, owing to the thermal expansion match between the chips and the board.
In order to physically attach and then electrically connect IC chips to a silicon wafer, three standard techniques have been successfully adapted from ceramic hybrid technology: flip-chip solder-bump reflow, wire bonding, and tape-automatic-bonding (TAB). The first listed of these methods, the solder bump method, is most relevant to the present invention. In this method, alternative layers of conductor and ceramic insulator are pressed together in the green state and fired to form a multilayer structure. Chips are provided with solder bumps on each pad and subsequently mounted upside down so that the solder bump positions on the chip correspond to interconnect areas on the ceramic multilayer.
It should not be forgotten that a main goal of the foregoing methods is to promote high speed devices. Reduced circuit dimensions act towards fulfillment of this goal. That is, to promote speed, it is desirable to interconnect chips with a minimum of capacitive loading and a minimum of interconnect length. Capacitive loading tends to slow down signal transmission such that high speeds attained on the chip cannot be maintained in communicating from one chip to another. Interconnection length between chips also contributes to propagation delay due to circuit length and also due to a self-inductance of the interconnection circuit.
Increasingly higher signal speeds have caused electrical problems to arise in the chip or die to substrate interface. These problems are particularly notable with greater than 250 MHz signals and in systems having both digital and analog signal components. Specifically, it has been found to be extremely difficult to minimize crosstalk between adjacent signal bumps and to maintain constant transmission line impedance as high speed signals traverse the interface of a die and substrate through a bump.
As bump construction plays a significant role in the present invention, some discussion of solder bump structure is appropriate here. Uniaxial solder bumps have been in use for many years and have found applicability in a wide variety of semiconductor chip to substrate or printed circuit board input/output (I/O) connections. Applications have been exploited in both the analog and digital interface areas. As technological advances have been and are continuing to be made in electronic systems with regard to higher frequency in analog applications and higher clock speed in digital systems, the standard uniaxial solder bump has been and continues to become an increasingly limiting portion of structures, especially with regard to crosstalk and impedance control. Additionally, there are emerging combined analog/digital hybrid systems where attractive applications for high speed signal processing exist but low crosstalk is essential at signal I/O's. Low crosstalk signals are extremely important where disparate signal levels are communicated via adjacent bumps. These situations arise in a variety of analog applications and in digital circuits where data signals are close to clock distribution bumps and power supply distribution bumps.
Thus, chip-to-board interconnection technology appears to be a weak point in terms of electrical performance and mechanical reliability of silicon hybrid wafer scale integration technology. It is a shortcoming and deficiency of the prior art that stringent requirements of low crosstalk and controlled impedance are not satisfactorily addressed by prior art solder bump interconnection methods.